As a result of the miniaturization pressure which is prevailing in the semiconductor industry, methods are needed with which so-called “3D Integrated Chips” (3D IC) can be produced. 3D ICs consist of chip stacks in which several chips are stacked vertically on top of one another and there are connections through the silicon to the vertically adjacent chips. The connections are called “Through Silicon Vias” (TSV).
These chips promise high packing density and higher performance at lower costs. Moreover, in this way new types and forms of chips can be produced. Fundamentally different methods are possible for producing 3D ICs, specifically the very time-consuming stacking of individual chips on individual chips, also called “Chip-to-Chip” (C2C) methods, or stacking of wafers on wafers, also called “Wafer to Wafer” (W2W) methods. Finally, the so-called “Chip to Wafer (C2W)” method is also discussed. A reasonable technical implementation has not been successful to date due to major technical problems. This invention relates to a technically feasible C2W method for producing 3D ICs.
Due to low throughput, C2C methods cause higher production costs and therefore may hardly be used in mass production.
W2W methods require that the two wafers have the same size and that the chips on the two wafers have the same size. The problem here is that the silicon utilization especially for higher chip stacks is below average (so-called yield). The attainable yield of functioning chips is lower than in C2C or C2W methods.
Technical problems in the implementation of a C2W method for producing chips stacks or 3D ICs are the handling of the wafers, especially with the chips stacked on them, and the varied requirements, especially temperatures, for the stacking process and for the connectors (interfaces) of the chips for mounting on circuit boards or fundamentally the higher-order packing unit.
Handling of the base wafer therefore acquires great importance because fracture of the base wafer shortly before separation of a plurality of chip stacks on the wafer would lead to scrapping of thousands of expensive chips. Handling of the base wafer with a plurality of chip stacks fixed/bonded thereon becomes more difficult, the thinner and/or greater the area of the base wafer. The base wafer is the wafer on which the chips are stacked in the C2W method.
US 2007/001281 A1 relates to a method for producing a semiconductor memory in which chips are stacked on the base wafer and then potted in resin to simplify production logistics in the production of memory chips. After potting, the memory chips are separated from their adjacent memory chips. In particular, different thermal expansions of the different materials of the diverse components present in the chip stacks are a problem during production, mainly when potting the memory chips and in the release from the carrier, and possible subsequent process steps.